More processors on SoCs means more sophisticated cache control. This article describes formal techniques for verifying cache coherency for the ARM AMBA AXI Coherency Extensions (ACE) protocol. Fig 1.
The use of on-chip cache memory helps design teams optimize multicore designs for both power and performance. While the use of hardware to implement cache coherency enables design teams to improve SoC ...
To view the multimedia news release, please go to: http://www.synopsys.com/Company/PressRoom/Pages/discovery-verification-ip-news-release.aspx “We have been users ...
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